Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create?
As a Senior RTL Design Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the micro-architecture and implementing the corresponding RTL for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team. You are expected to lead, understand and debug system-level issues. You will do evaluations of new prototyping and emulation platforms from various vendors and architect/implement them to meet our needs. You will participate in the lab bring-up of these blocks either in an FPGA or silicon by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will:
· Design world class hardware and software
· Communicate and work with team members across multiple disciplines
· Develop detailed design specifications and documentation
· Perform RTL coding and synthesis
· Work with Partners/Supplier to optimize and customize their products
· Run industry standard code quality tools and fix issues found by them
· Develop all aspects of Field Programmable Gate Array (FPGA) implementation, including design partitioning, synthesis, place and route, timing analysis, IP integration, RTL simulation, timing closure and system level debugging.
· Debug test failures on emulation and FPGA systems
· Participate in test plan and coverage reviews
The ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages. They should have developed complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. They should be familiar with modern SoC architectures, various interconnect topologies such as AMBA AXI, APB, AHB, and implementations. Experience with I/O interfaces such as SPI, I2C, I2S, PDM, and MIPI CSI/DSI/Slimbus/Soundwire is also preferred. Experience with memory instantiation and memory compilers is also preferred. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues.