• PCIe RTL Design Engineer

    Location US-TX-Austin
    Posted Date 2 weeks ago(11/6/2018 9:54 AM)
    Job ID
    Annapurna Labs (U.S.) Inc.
    Company/Location (search) : Country (Full Name)
    United States
  • Job Description

    Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. We are seeking experienced RTL Design Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we’re handling massive scale and rapid integration of emergent technologies.

    As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in the application of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve your product’s performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

    Key Responsibilities:
    • Work with SOC and system architects to define product strategy and architecture of PCIe subsystem solution
    • Lead our PCIe design efforts
    • Perform RTL coding and micro architecture tasks
    • Instruct Physical design team with physical constraints, timing analysis and signoff responsibilities for your Block
    • Support the verification team with by developing verification strategies, debug and provide coverage definitions
    • Participate in test plan and coverage reviews
    • Participate in the definition of the SoC Lab testing of the product
    • Provide technical leadership through personal example, mentorship, and strong teamwork

    Basic Qualifications

    • BSc + 8yrs or MSc + 6yrs in EE/CS
    • VLSI engineering background, with 6+ years of experience as block RTL design
    • 4+ years of experience with the design and integration of PCIe subsystem solutions
    • Lab experience with the bringup and validation of PCIe subsystem solutions, experience with PCIe protocol analysis tools

    Preferred Qualifications

    • Large breadth of knowledge from architecture through physical design
    • Experience with PCIe SERDES
    • Previous experience with full chip timing constraints definition and timing path analysis
    • Familiarity solving physical design challenges for PCIe or other high speed solutions
    • Previous experience with technical leading positions
    • Previous experience mentoring and instructing other team members
    • Previous experience with System Verilog and System Verilog interfaces
    • Previous experience with AXI/APB bus-protocols and data movement
    • Previous experience with variety of low power design techniques

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