• RTL Design Engineer

    Location US-TX-Austin
    Posted Date 2 weeks ago(11/6/2018 9:54 AM)
    Job ID
    743981
    Company
    Annapurna Labs (U.S.) Inc.
    Company/Location (search) : Country (Full Name)
    United States
  • Job Description

    Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. We are seeking experienced RTL Design Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we’re handling massive scale and rapid integration of emergent technologies.

    As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in the application of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve your product’s performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

    Key Responsibilities:
    • Work with SOC design leaders and colleagues to define block level specifications
    • Perform RTL coding for blocks
    • Work with physical design team to define physical constraints and timing analysis requirements for your block
    • Support the verification team with by developing verification strategies, debug and provide coverage definitions
    • Participate in verification test plan and coverage reviews


    Basic Qualifications


    • BSc + 2yrs or MSc in EE/CS
    • VLSI engineering background with experience in RTL design
    • Previous experience and familiarity with code quality tools such as Spyglass LINT and CDC

    Preferred Qualifications



    • Previous experience solving physical design challenges
    • Previous experience with System Verilog and System Verilog interfaces
    • Good familiarity with automation and scripting languages (Perl/Tcl/Python)

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