• Physical Design Engineer

    Location US-CA-Cupertino
    Posted Date 4 days ago(4 days ago)
    Job ID
    718152
    Company
    Annapurna Labs (U.S.) Inc.
  • Job Description

    Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. We are seeking experienced Physical Design Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we’re handling massive scale and rapid integration of emergent technologies.

    As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in the application of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve your product’s performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

    Key Responsibilities:
    • Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure
    • Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off
    • Develop physical design methodologies
    • Evaluate 3rd party IP and provide recommendations
    • Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams


    Basic Qualifications

    • BS + 10yrs or MS + 8yrs in EE/CS
    • 6+ years of experience in ASIC Physical Design from RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm
    • Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
    • Scripting experience with Tcl, Perl or Python

    Preferred Qualifications

    • Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
    • 4+ years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain.
    • Thorough knowledge of device physics, custom/semi-custom implementation techniques
    • Experience solving physical design challenges across various technologies such as DDR, PCIe, fabrics etc.
    • Experience in extraction of design parameters, QOR metrics, and analyzing trends
    • Ability to provide mentorship, guidance to junior engineers and be a very effective team player
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