• Senior Design Verification Engineer

    Location US-TX-Austin
    Posted Date 1 month ago(1 month ago)
    Job ID
    707267
    Company
    Annapurna Labs (U.S.) Inc.
  • Job Description

    Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. We are seeking experienced Hardware Design Engineers to build the next generation of our cloud server infrastructure. Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies.

    As a member of the Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in the application of new technologies to large scale server deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve your products performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

    Responsibilities:
    · Verify and validate that our hardware and software solutions will achieve the functionality needed to enable our customers
    · Develop a deep understanding of the end customer requirements, including software applications, use models, system architecture and the SoC architecture/micro-architecture of our solutions
    · Develop multi-faceted verification/validation strategies and plans that include advanced design verification, FPGA, emulation, software and full system testing
    · Efficiently execute test plans on multiple platforms, measure progress and metrics, and work with cross-functional teams to achieve these results

    Basic Qualifications

    · BS degree or higher in EE or CE
    · 8+ years or more of practical semiconductor design verification experience using System Verilog and UVM
    · Experience developing and executing test plans for IP level and/or SOC level verification
    · Ownership of testbench development, including stimulus, checkers, assertions and coverage.
    · Experience identifying bugs in architecture, algorithms, functionality and performance with strong overall debug skills
    · Experience using multiple verification platforms: FPGA, emulator, software environments and/or post-silicon

    Preferred Qualifications

    · Proficient with C/C++
    · Proficient with scripting languages (Python or Perl) for automation
    · Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
    · Experience with industry standard I/O interfaces
    · Experience with formal verification
    · Experience with embedded software
    · Experience as a technical lead mentoring other engineers


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