• Physical Design Leader

    Location US-TX-Austin
    Posted Date 10 months ago(9/20/2017 9:09 AM)
    Job ID
    Annapurna Labs (U.S.) Inc.
  • Job Description

    Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. We are seeking experienced Physical Design Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we’re handling massive scale and rapid integration of emergent technologies.

    As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in the application of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve your product’s performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

    Key Responsibilities:
    · Lead a physical design team from RTL-to-GDSII resulting in leading-edge semiconductor products
    · Define and drive flows methodologies to optimized physical design work, define guidelines and checklists, drive execution, and track progress
    · Lead Synthesis and place & route efforts creating an efficient and high performing team.
    · Define project plans, goals and milestones for both short and long-term work with optimized dependencies between different domains
    · Resolve design and flow issues related to physical design through the identification of potential solutions and drive resolution
    · Work with the front-end teams to understand chip architecture and drive physical aspects early in the definition cycle
    · Define and implement breakthrough productivity using cloud computing
    · Full responsibility of RTL-to-GDSII, SignOff and Tape out workflow and execution
    · Be a highly-valued member of our start-up like team through excellent collaboration and teamwork across disciplines
    · Hire and Develop the Best: hire the industry’s best talent and mentor, build expertise, and grow each team member

    Basic Qualifications

    · BS degree or higher in EE, CE, or CS
    · 10+ years of hands-on experience in physical design and large chip integration
    · 5+ years of experience leading successful physical design teams including several leading-edge product’s tape-out and production ramp
    · Experience with all aspects of ASIC integration including floor planning, clock and power design, I/O planning and hard IP integration
    · Familiar with hierarchical design approach, budgeting, timing and physical convergence, multi Vt strategies, voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions
    · Familiar with ECO flow and netlist/metal based logic modifications
    · Strong communication, time management and technical skills
    · Broad experience including high speed, low power, low cost, with large and small SoC designs utilizing the latest state of the art technology nodes

    Preferred Qualifications

    · Must have experience in integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain
    · Experienced working with SI and packaging engineers
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