• Physical Design Engineer

    Location US-TX-Austin
    Posted Date 4 months ago(3/23/2018 6:47 AM)
    Job ID
    Annapurna Labs (U.S.) Inc.
  • Job Description

    Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. We are seeking experienced Physical Design Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we’re handling massive scale and rapid integration of emergent technologies.

    As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in the application of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve your product’s performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

    Key Responsibilities:
    · Work with our front-end design and physical design teams to develop leading-edge physical implementations and silicon products
    · Expand your in-depth understanding and experience with physical design tools and flows – from RTL to GDS
    · Your work will focus on the full development flow: Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off
    · Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL design team
    · Flow development, Innovation, optimization and scripting

    Basic Qualifications

    · BS degree or higher in EE, CE, or CS
    · 10+ years of experience as a physical design engineer with expertise in RTL-to-GDSII flow, floor planning, Clock tree synthesis and block-level/chip-level signoff
    · Broad experience including high speed, low power, low cost, with large and small SoC designs utilizing the latest state of the art technology nodes
    · Successfully complete several product development cycles
    · Strong communication, time management and technical skills
    · Expertise using leading-edge EDA tools (Synopsys, Cadence or Mentor Graphics)
    · Ability to provide mentorship and guidance to junior engineers and be a very effective team player
    · Excellent verbal and written communication skills

    Preferred Qualifications

    · Experience in integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain
    · Ability to plan, execute, course correct and optimize blocks and SoC level implementations
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